Embodiments relate to storage of information associated with transactions within a system.
In many different systems, an interface may be coupled between a processor and memory. Some systems may use a memory controller for this interface, while other systems, including many multiprocessor systems may include a node controller that can provide an interface between multiple processors and an associated memory, which may be formed of one or more memory devices such as dual in-line memory module (DIMM) chips.
This interface between processor and memory, whether as a memory controller or as a node controller, often includes a data buffer to temporarily store incoming transactions and associated data until the transactions are completed. Oftentimes such a buffer may include multiple incoming and outgoing (i.e., read and write) ports. Even if the aggregate bandwidth of the agents and the ports on the buffer are same, traffic congestion can occur because multiple agents may be sending transactions simultaneously. This can be solved by increasing the number of ports of such a buffer, so that more transactions may be handled. However, a buffer with more ports has lower efficiency in terms of bit cell area. Also this kind of approach leads to routing congestion within a chip.
Another approach could be matching aggregate bandwidth of a data buffer and agents on both sides of the data buffer. However, this would require multiplexing data streams while writing into the buffer and demultiplexing while reading from the buffer. In a given system implementation, back pressure while writing from one side or both sides of the buffer can occur. As a result, one or more rate matching buffers may be needed in addition to the data buffer to temporarily store data in case there are more read (or write) transactions in a given cycle than the number of available ports in the buffer. Such rate matching buffers add latency to the transaction paths. Accordingly, interfaces may suffer from increased power consumption, increased latency and greater chip area.